Xueqing Li 李学清
Associate Professor, Ph.D. 副教授
Research Interests
Data-oriented chip-algorithm co-design for AI computing acceleration, with particular interests in CMOS and beyond-CMOS circuits and systems to enable "More than Moore" and "Beyond Moore". Memory-centric computing, a.k.a. compute-in-memory and process-in-memory, against "the memory wall"; Low-power embedded memory featured with non-volatility, reliability, and its synergy with various intelligent tasks; Other related analog, digital and mixed-signal circuits. Mixed-signal CMOS IC design D/A converters
Appointment and Education
- Tenured Associate Professor (2024–present), The Department of Electronic Engineering, Tsinghua University, Beijing, China
- Head of EE Dept. Student Affairs Office (2022–present), 清华大学电子系党委学生工作组长、党委副书记
- Tenure-track Associate Professor (2021–2024), The Department of Electronic Engineering, Tsinghua University, Beijing, China
- Tenure-track Assistant Professor (2018–2020), The Department of Electronic Engineering, Tsinghua University, Beijing, China
- PostDoc Associate (2013–2017), EECS, The Pennsylvania State University, USA
- Ph.D. (2007–2013), The Department of Electronic Engineering, Tsinghua University, Beijing, China
Thesis: Wideband High-Dynamic-Range D/A Converter Design - B.S. (2003–2007), Department of Electronic Engineering, Tsinghua University, Beijing, China
Selected Publications
A Full-Digital Heterogenous Computing-in-Memory with Dual-Bit Serialized Weight Stream and Ping-Pong Computing for Efficient Transformer Acceleration
IEEE Transactions on Circuits and Systems I: Regular Papers
HEIRS-PS: Hybrid Three-dimensional RRAM- and SRAM-CIM for Pipelined Sparse Multi-Task Transformer Acceleration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Folded-Differential Switched-Capacitor SRAM CIM Macro With Scalable MAC Sizes for TinyML Inference
IEEE SOLID-STATE CIRCUIT LETTERS
From Analog to Digital-Assisted Techniques: Modern RF DAC Design for High Speed and Dynamic Range
Electromagnetic Science
ROM-SRAM Hybrid Compute-in-Memory for Edge AI: Circuits, Architectures and Challenges
The Journal of Supercomputing
FSDB: A Folded-Store Dynamic-Broaden Hybrid Compute-in-ROM/SRAM Architecture for Deploying Large-Scale DNNs On-Chip
Design, Automation & Test in Europe Conference & Exhibition (DATE)
EGO: Efficient Compression of Unstructured Sparse DNNs for Compute-in-Memory based on Graph Minimum-Cost Matching Optimization
Design, Automation & Test in Europe Conference & Exhibition (DATE)
A Heterogeneous CIM Architecture with Splittable Non-Volatile Computing-in-SRAM Cell-Pairs Enabling Efficient On-Chip Neural Network Inference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An NVM Non-Idealities Mitigation Solution Using Cell-Clustered Calibration for Analog High-Density Edge Multi-Level Cell Compute-in-Memory
IEEE Transactions on Circuits and Systems I: Regular Papers
Charge-domain content addressable memory based on ferroelectric capacitive memory for reliable and energy-efficientone-shot learning
Nature Communications
A 28nm 68.6TOPS/W Folded-Differential Switched-Capacitor FIA-Based SRAM CIM Macro with Scalable Mac Sizes for Tiny-ML Inference
IEEE Asian Solid-State Circuits Conference (ASSCC)
A 28nm 26.9 Mb/mm² x 43.1 TOPS/W Fully Digital Task-Flexible Compute-in-ROM/SRAM Macro for Energy-Efficient Edge AI Inference
The 1st IEEE Cross-Disciplinary Conference on Memory-Centric Systems (CCMCC 2025)
SPIDER: A Sparsity-Aware High-Density Compute-in-ROM Architecture for Large-Scale Nerual Networks On-Chip Deployment
The 1st IEEE Cross-Disciplinary Conference on Memory-Centric Systems (CCMCC 2025)
An Area-efficient Look-up-table-based eDRAM Digital CIM Macro for Neural Network Inference
IEEE Journal of Solid-State Circuits
A review on ROM-SRAM hybrid compute-in-memory architecture
Integrated Circuits and Embedded Systems
DCiROM: A High-Density Fully-Digital Compute-in-Read-Only-Memory Macro for Energy-Efficient Task-Level DNN Inference
IEEE Transactions on Circuits and Systems I: Regular Papers
DANCE: Dual-Side Agile N:M Sparse Compressed Digital CiM Accelerator for Efficient Compound AI
ICCAD2025
A 16-Bit 10-GS/s DAC Achieving > 65 dBc SFDR and < -75 dBc IM3 up to the Nyquist in 28nm CMOS
IEEE Journal of Solid-State Circutis
A 28nm 8-Bit 32-GS/S DAC Achieving > 55dBc/> 40dBc SFDR Up to 5.2GHz/13.6GHz Using 4-Channel NRZ Time-Interleaving with Background Calibration for Direct Digital Signal Synthesis
IEEE European Solid-State Electronics Research Conference (ESSERC)
Enabling Energy-Efficient and High-Density eDRAM-LUT-Based Computing-in-Memory Using Anti-Ferroelectric Transistors
IEEE European Solid-State Electronics Research Conference (ESSERC)
Honors and Awards
- 2026 National Career Award (2026年国家高层次人才计划入选）
- 2026 DATE2026 Best Paper Award on high-density ROM-SRAM CiM (Student Tianyi Yu et al).
- 2026 ICAC2026 Best Student Poster Award on high-performance D/A converter design (Student Kezhuo Ma).
- 2025 BEST IEEE CEDA Ph.D. FORUM AWARD (Student Jianfeng Wang)
- 2025 China Association for Science and Technology (Taixin Li, 中国科协青年科技人才培育工程博士生)
- 2025 National Natural Science Foundation of China (NSFC) for Youth Student Basic Research Project (Doctoral Student)（Taixin Li, 国家自然科学基金青年学生基础研究项目-博士研究生）
- 2025 Beijing Natural Science Foundation Undergraduate "Qiyan" Program (Xinyu Zhou, 北京市自然科学基金本科生“启研”计划)
- 2025 Tsinghua University First-Class Teaching Achievement Award (2025年清华大学教学成果一等奖，电子信息学科“双课堂协同”实践育人新模式探索与实践, 排名第四)
- 2024 Tsinghua University Outstanding Teaching Award (清华大学2024年度教学优秀奖)
- 2024 Beijing Excellent Textbook Award
- 2024 ZHOU Bingkun Scholar Award of THU-EE (清华大学周炳琨学者) [ News-link ]
- 2024 ACM Student Research Competition (SRC) Award (Student Jianfeng Wang)