Scholarship
Publications
Peer-reviewed papers from NICS-AIM, grouped by year.
2026
9 papers-
A Full-Digital Heterogenous Computing-in-Memory with Dual-Bit Serialized Weight Stream and Ping-Pong Computing for Efficient Transformer Acceleration
-
HEIRS-PS: Hybrid Three-dimensional RRAM- and SRAM-CIM for Pipelined Sparse Multi-Task Transformer Acceleration
-
A Folded-Differential Switched-Capacitor SRAM CIM Macro With Scalable MAC Sizes for TinyML Inference
-
From Analog to Digital-Assisted Techniques: Modern RF DAC Design for High Speed and Dynamic Range
-
ROM-SRAM Hybrid Compute-in-Memory for Edge AI: Circuits, Architectures and Challenges
-
FSDB: A Folded-Store Dynamic-Broaden Hybrid Compute-in-ROM/SRAM Architecture for Deploying Large-Scale DNNs On-Chip
-
EGO: Efficient Compression of Unstructured Sparse DNNs for Compute-in-Memory based on Graph Minimum-Cost Matching Optimization
-
A Heterogeneous CIM Architecture with Splittable Non-Volatile Computing-in-SRAM Cell-Pairs Enabling Efficient On-Chip Neural Network Inference
-
An NVM Non-Idealities Mitigation Solution Using Cell-Clustered Calibration for Analog High-Density Edge Multi-Level Cell Compute-in-Memory
2025
25 papers-
Charge-domain content addressable memory based on ferroelectric capacitive memory for reliable and energy-efficientone-shot learning
-
A 28nm 68.6TOPS/W Folded-Differential Switched-Capacitor FIA-Based SRAM CIM Macro with Scalable Mac Sizes for Tiny-ML Inference
-
A 28nm 26.9 Mb/mm² x 43.1 TOPS/W Fully Digital Task-Flexible Compute-in-ROM/SRAM Macro for Energy-Efficient Edge AI Inference
-
SPIDER: A Sparsity-Aware High-Density Compute-in-ROM Architecture for Large-Scale Nerual Networks On-Chip Deployment
-
An Area-efficient Look-up-table-based eDRAM Digital CIM Macro for Neural Network Inference
-
DCiROM: A High-Density Fully-Digital Compute-in-Read-Only-Memory Macro for Energy-Efficient Task-Level DNN Inference
-
DANCE: Dual-Side Agile N:M Sparse Compressed Digital CiM Accelerator for Efficient Compound AI
-
A 16-Bit 10-GS/s DAC Achieving > 65 dBc SFDR and < -75 dBc IM3 up to the Nyquist in 28nm CMOS
-
A 28nm 8-Bit 32-GS/S DAC Achieving > 55dBc/> 40dBc SFDR Up to 5.2GHz/13.6GHz Using 4-Channel NRZ Time-Interleaving with Background Calibration for Direct Digital Signal Synthesis
-
Enabling Energy-Efficient and High-Density eDRAM-LUT-Based Computing-in-Memory Using Anti-Ferroelectric Transistors
-
A 7T2C Pixel Circuit Compensating for TFT Threshold Voltage in Active-Matrix Simultaneous Neurostimulation
-
Hybrid SRAM/ROM Compute-in-Memory Architecture for High Task-Level Energy Efficiency in Transformer Models with 8928-kb/mm2 Density in 28-nm CMOS
-
18-3: Pro-Cache-CIM: A 28nm 69.4TOPS/W Product-Cache-based Digital-Compute-in-Memory Macro Leveraging Data Locality Pattern in Vision AI tasks
-
ADDR: Architecture Design and Model Deployment Optimization for Hybrid SRAM-ROM Compute-in-Memory
-
Kung-Fu: An Energy-Efficient Compute-in-Memory Approach for Neural Network Inference Using Multi-Level Binary Computing Fusion
-
3D-Domino: Ultra-Dense High-Accuracy 3D eDRAM-ROM Compute-in-Memory Based on CAA-IGZO TFT for Edge Large-Scale Model Inference
-
LTPS-TFT-Based In-Sensor Compression with Spatiotemporal Differencing Optimization
-
PUFiM: A Robust and Efficient FeFET-Based Security Solution Merging Physical Unclonable Function with Compute-in-Memory for Edge AI
-
DIAS: Distance-based Attention Sparsity for Ultra-Long-Sequence Transformer with Tree-like Processing-in-Memory Architecture
-
DSC-ROM: A Fully Digital Sparsity-Compressed Compute-in-ROM Architecture for On-Chip Deployment of Large-Scale DNNs
-
A 28nm 8-Bit 16-GS/s DAC with >60dBc/>40dBc SFDR up to 2.3GHz/5.4GHz Using 4-Channel NRZ-Output-Overlapped Time-Interleaving
-
3D-METRO: Deploy Large-Scale Transformer Model on A Chip Using Transistor-Less 3D-Metal-ROM-Based Compute-in-Memory Macro
-
DCiROM: A Fully Digital Compute-in-ROM Design Approach to High Energy Efficiency of DNN Inference at Task Level
2024
21 papers-
Demonstration of high-reconfigurability and low-power strong physical unclonable function empowered by FeFET cycle-to-cycle variation and charge-domain computing
-
First Demonstration of AFeFET-Based Capacitor-Less eDRAM Computing-in-Memory Featuring 4.84 Mb/mm^2 High Memory Density, 10^5 s Long Retention Time, and >10^10 High Endurance
-
CiMSAT: Exploiting SAT Analysis to Attack Compute-in-Memory Architecture Defenses
-
A Multiply-less Approximate SRAM Compute-In- Memory Macro for Neural-Network Inference
-
REMNA: Variation-Resilient and Energy-Efficient MLC FeFET Computing-in-Memory Using NAND Flash-Like Read and Adaptive Control
-
NAND-Tree: A 3D NAND Flash Based Processing In Memory Accelerator for Tree-Based Models on Large-Scale Tabular Data
-
Cross-Layer Exploration and Chip Demonstration of In-Sensor Computing for Large-Area Applications with Differential-Frame ROM-Based Compute-In-Memory
-
HEIRS: Hybrid Three-Dimension RRAM- and SRAM-CIM Architecture for Multi-task Transformer Acceleration
-
A 1024-Channel Neurostimulation System Enabled by Photolithographic Organic Thin-Film Transistors with High Uniformity
-
A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS
-
A 28nm 8928Kb/mm2-weight-density hybrid SRAM/ROM Compute-in-Memory architecture reducing >95% weight loading from DRAM
-
A Module-Level Configuration Methodology for Programmable Camouflaged Logic
-
TFT-Based Near-Sensor In-Memory Computing: Circuits and Architecture Perspectives of Large-Area eDRAM and ROM CiM Chips
-
TroScan: Enhancing On-Chip Delivery Resilience to Physical Attack through Frequency-Triggered Key Generation
-
CafeHD: A Charge-Domain FeFET-Based Compute-in-Memory Hyperdimensional Encoder with Hypervector Merging
-
ULSeq-TA: Ultra-Long Sequence Attention Fusion Transformer Accelerator Supporting Grouped Sparse Softmax and Dual-Path Sparse LayerNorm
-
Cramming More Weight Data onto Compute-in-Memory Macros for High Task-Level Energy Efficiency Using Custom ROM with 3984Kb/mm2 Density in 65nm CMOS
-
An Energy-Efficient Computing-in-Memory NN Processor with Set-Associate Block-Wise Sparsity and Ping-Pong Weight Updating
-
A Low-Temperature Poly-Silicon Thin Film Transistor Pixel Circuit for Active-Matrix Simultaneous Neurostimulation
-
ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns
2023
23 papers-
30 Mb/mm2/layer 3D eDRAM Computing-in-Memory with Embedded BEOL Peripherals and Local Layer-wise Calibration based on First-Demonstrated Vertically- stacked CAA-IGZO 4F2 2T0C Cell
-
基于铁电晶体管的存储与存算一体电路(Memory and Compute-in-Memory Based on Ferroelectric Field Effect Transistors)
-
A 7nm 10TFLOPS Datacenter-Oriented GPU with 4-Corner Stacked 64GB Memory by The Means of 2.5D Packaging Technology
-
Lowering Latency of Embedded Memory by Exploiting In-Cell Victim Cache Hierarchy Based on Emerging Multi-Level Memory Devices
-
TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations
-
A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro
-
GRAPHIC: Gather and Process Harmoniously in the Cache with High Parallelism and Flexibility
-
ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-based Memories
-
A 66.67kHz 4.953 nJ/Conv-Step 5b Fully Integrated Asynchronous SAR ADC Using 4μm LTPS TFTs
-
Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays
-
Fe-GCN: A 3D FeFET Memory Based PIM Accelerator for Graph Convolutional Networks
-
CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration
-
A 2-Transistor-2-Capacitor Ferroelectric Edge Compute-in-Memory Scheme with Disturb-Free Inference and High Endurance
-
SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity-Compensated Fully-Parallel Analog Adder Tree
-
WeightLock: a Mixed-Grained Weight Encryption Approach Using Local Decrypting Units for Ciphertext Computing in DNN Accelerators
-
FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access with Reduced Bitline Charging Activity and Recycled Bitline Charge
-
Victor: A Variation-resilient Approach Using Cell-clustered Charge-domain computing for High-density High-throughput MLC CiM
-
ASMCap: An Approximate String Matching Accelerator for Genome Sequence Analysis Based on Capacitive Content Addressable Memory
-
A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse Digital Architecture
-
A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference
-
A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC Achieving >70dBc SFDR and <-80dBc IM3 up to 1GHz with Enhanced Constant-Switching-Activity Data-Weighted-Averaging
-
A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration
-
FAST: A Fully-Concurrent Access SRAM Topology for High Row-wise Parallelism Applications Based on Dynamic Shift Operations
2022
12 papers-
On the Write Schemes and Efficiency of FeFET 1T NOR Array for Embedded Nonvolatile Memory and Beyond
-
CapCAM: A Multi-Level Capacitive Content Addressable Memory for High-Accuracy and High-Scalability Search and Compute Applications
-
Hidden-ROM: A Compute-in-ROM Architecture to Deploy Large-Scale Neural Networks on Chip with Flexible and Scalable Post-Fabrication Task Transfer Capability
-
High-density energy-efficient charge-domain computing based on CAA-IGZO TFT with BEOL-compatible 3D integration
-
A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface
-
YOLoC: DeploY Large-Scale Neural Network by ROM-based Computing-in-Memory using ResiduaL Branch on a Chip
-
CREAM: Computing in ReRAM-assisted Energy and Area-efficient SRAM for Neural Network Acceleration
-
Computing-in-Memory with Thin-Film-Transistors: Challenges and Opportunities
-
STICKER-IM: A 65nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse
-
An 8T/Cell FeFET-Based Nonvolatile SRAM with Improved Density and Sub-fJ Backup and Restore Energy
-
PACA: A Pattern Pruning Algorithm and Channel-Fused High PE Utilization Accelerator for CNNs
2021
15 papers-
High Area/Energy Efficiency RRAM CNN Accelerator with Pattern-Pruning-Based Weight Mapping Scheme
-
A 65nm Energy-Efficient Inter-Frame Data Reuse Neural Network Accelerator for Video Applications
-
Low-Power and Scalable Retention-Enhanced IGZO TFT eDRAM-Based Charge-Domain Computing
-
DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays
-
Analysis of Using Negative Capacitance FETs to Optimize Linearity Performance for Voltage Reference Generators
-
Almost-Nonvolatile IGZO-TFT-Based Near-Sensor In-Memory Computing
-
Dynamic Switching Sequence to Compensate the Integral Nonlinearity in Current-steering DACs
-
Reducing Signal Swing Overheads to only 8% in Background 3rd-order Inter-Stage Gain Error Calibration for Pipeline ADCs
-
Dynamic Ternary Content-Addressable Memory Is Indeed Promising: Design and Benchmarking Using Nanoelectromechanical Relays
-
A 2.75-to-75.9 TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating
-
STICKER-T: An Energy Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration
2020
15 papers-
Design Insights of Non-volatile Processors and Accelerators in Energy Harvesting Systems
-
Guidelines for Ferroelectric FET Reliability Optimization: Charge Matching
-
FeFET-Based Low-Power Bitwise Logic-in-Memory with Direct Write-Back and Data-Adaptive Dynamic Sensing Interface
-
High PE Utilization CNN Accelerator with Channel Fusion Supporting Pattern-Compressed Sparse Neural Networks
-
One-Shot Refresh: A Low-Power Low-Congestion Approach for Dynamic Memories
-
Challenges and Trends in Developing Nonvolatile Memory Enabled Computing Chips for Intelligent Edge Devices
-
A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse
-
A 65nm 24.7 uJ/Frame 12.3 mW Activation Similarity Aware Convolutional Neural Network Video Processor Using Hybrid Precision Inter Frame Data Reuse and Mixed-Bit-Width Difference Frame Data Codec
-
Integrated CAM-RAM Functionality using Ferroelectric FETs
-
Mismatch of Ferroelectric Film on Negative Capacitance FETs Performance
-
Adaptive Circuit Approaches to Low-Power Multi-Level/Cell FeFET Memory
-
Design of Almost-Nonvolatile Embedded DRAM Using Nanoelectromechanical Relay Devices
-
STICKER: An Energy Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65nm CMOS
-
Utilization of Negative Capacitance FETs to Boost Analog Circuit Performances
2019
10 papers-
Enabling New Computing Paradigms with Emerging Symmetric-Access Memories
-
A 1.8mW Perception Chip with Near-Sensor Processing Scheme for Low-Power AIoT Applications
-
A 3T/Cell Practical Embedded Nonvolatile Memory Supporting Symmetric Read and Write Access Based on Ferroelectric FETs
-
A 16b Clockless Digital-to-Analog Converter with Ultra-Low-Cost Poly Resistors Supporting Wide-Temperature Range from -40°C to 85°C
-
A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural-Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1x Higher TOPS/mm2 and 6T HBST-TRAM-Based 2D Data-Reuse Architecture
-
ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-memory Computation Support
-
AERIS: Area/Energy-Efficient 1T2R ReRAM Based Processing-in-Memory Neural Network System-on-a-Chip
-
Sensing in Ferroelectric Memories and Flip-Flops
2018
14 papers-
A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System
-
A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support
-
Neofog: Nonvolatility-exploiting optimizations for fog computing
2017
10 papers-
Spendthrift: Machine Learning Based Resource and Frequency Scaling for Ambient Energy Harvesting Nonvolatile Processors
-
Maximum Energy Efficiency Tracking Circuits for Converter-less Energy Harvesting Sensor Nodes
-
A 130nm FeRAM-based parallel recovery nonvolatile SOC for normally-OFF operations with 3.9x faster running speed and 11x higher energy efficiency using fast power-on detection and nonvolatile radio controller