Research direction
Data-oriented Chip-Algorithm Co-design for AI Computing Acceleration
Compute-in-memory, process-in-memory, low-power embedded memory, and related circuits for AI acceleration.
Our research in chip-algorithm co-design focuses on bridging the gap between AI algorithms and their hardware implementations. We develop novel compute-in-memory (CiM) and process-in-memory (PiM) architectures that fundamentally rethink the von Neumann bottleneck.
Key research areas include:
- Ferroelectric capacitor-based compute-in-memory for edge AI inference
- Hybrid SRAM/ROM CiM for transformer model acceleration
- High-density ROM-based CiM with multi-bit precision
- 3D-stacked CiM architectures for high-bandwidth data access
- Algorithm-hardware co-optimization for sparse neural networks
- Charge-domain content-addressable memory for associative computing
Our work spans from device-level innovation (FeFET, IGZO) to system-level integration, targeting applications in large language models, computer vision, and IoT edge intelligence. We collaborate closely with foundries and EDA tool vendors to bridge the gap between research prototypes and practical deployment.